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    Product产品详细

  • 名称:
    必威注册_betway体育手机版_必威体育官网
    型号:
    S5GT(Part No:T0119)
    规格:
    5SGTMC7K3F40C2N
    品牌:
    Altera
    价格:
    116955.00 元
    分享到:

    【英文】

    Transceiver Signal Integrity Development Kit, Stratix V GT Edition

    The Altera® Stratix® V GT Transceiver Signal Integrity (SI) Development Kit provides a platform for electrical compliance testing and interoperability analysis. The accessibility to multiple channels allows for real-world analysis as implemented in the system with transceiver channels available through SMA and popular backplane connectors. You can use this development kit to perform the following tasks:

  • Evaluate transceiver link performance up to 28 Gbps
  • Generate and check pseudo-random binary sequence (PRBS) patterns via a simple to use GUI (does not require the Quartus® II software)
  • Access advanced equalization to fine tune link settings for optimal bit error ratio (BER)
  • Perform jitter analysis
  • Verify physical media attachment (PMA) interoperability with Stratix V GT FPGAs for targeted protocols, such as CEI-25/28G, CEI-11G, PCI Express® (PCIe®) Gen 3.0, 10GBASE-KR, 10 Gigabit Ethernet, XAUI, CEI-6G, Serial RapidIO® , HD-SDI, and others
  • Use the built-in high speed backplane connectors to evaluate custom backplane performance and evaluate link BER
  • 产品规格

    Featured device

  • 5SGTMC7K3F40C2N
  • Configuration status and set-up elements

  • JTAG
  • On-board USB-BlasterTM
  • Fast passive parallel (FPP) configuration via MAX® II device and flash memory
  • Two configuration file storage
  • Temperature measurement circuitry (die and ambient temperature)
  • Clocks

  • 50 MHz, 125 MHz, programmable oscillators (preset values: 624 MHz, 644.5 MHz, 706.25 MHz, and 875 MHz)
  • SMA connectors for supplying an external differential clock to transceiver reference clock
  • SMA connectors for supplying an external differential clock to the FPGA fabric
  • SMA connectors to output a differential clock from the FPGA's phase-locked loop (PLL) output pin
  • General user input/output

  • 10-/100-/1000-Mbps Ethernet PHY (RGMII) with RJ-45 (copper) connector
  • 16x2 character LCD
  • One 8-postion dipswitch
  • Eight user LEDs
  • Four user pushbuttons
  • Memory devices

  • 128-megabyte (MB) sync flash memory (primarily to store FPGA configurations)
  • High speed serial interfaces

  • Four full-duplex GTB (28.05 Gbps) transceiver channels routed to MMPX connectors
  • Seven full-duplex GXB (12.5 Gbps) transceiver channels routed to SMA connectors
  • Short trace routed on a micro-strip
  • Six strip-line channels from the with all the trace lengths are matched across channels
  • 21 full-duplex GXB transceiver channels routed to backplane connector
  • Seven channels to Molex® Impact® connector
  • Seven channels to Amphenol® XCede®
  • Seven channels to footprint of Tyco Strada® Whisper® (connector is not populated)
  • Power

  • Laptop DC input
  • Voltage margining
  • Stratix V GX Transceiver Signal Integrity Development Board Block Diagram

    组件配置


    包装内容

  • Altera's Complete Design Suite (download from Altera download center )
  • Quartus II software includes support for Stratix V FPGAs
  • 1-year license included
  • Nios® II Embedded Design Suite
  • MegaCore® intellectual property (IP) library includes PCIe, Triple-Speed Ethernet, Serial Digital Interface (SDI), and DDR3 SDRAM High-Performance Controller MegaCore IP cores
  • IP evaluation available through OpenCore Plus
  • Board Update Portal
  • Featuring Nios II web server and remote system update
  • GUI-based Board Test System
  • Interfaces to PC via JTAG
  • User controllable PMA settings (pre-emphasis, equalization, and so on)
  • Status indication (errors, BER, and so on)
  • Complete documentation
  • User guide
  • Reference manual
  • Board schematics and layout design files
  • 【中文】

    Stratix V GT 版收发器信号完整性开发套件

    Stratix® V GT收发器信号完整性(SI)开发套件为电信号兼容性测试和互操作性分析提供了平台。您可以对多个通道进行实际分析,通过SMA以及流行的背板连接器使用在系统中实现的这些收发器通道。采用这一开发套件,您能够完成以下任务:
    评估性能高达28 Gbps的收发器链路
    通过使用方便的GUI (不需要Quartus® II软件)来生成并检查伪随机二进制序列(PRBS)码型
    使用高级均衡功能,精细的调整链路设置,降低误码率(BER)。
    进行抖动分析
    采用Stratix V GT FPGA,针对目标协议,验证物理介质附加(PMA)子层的互操作性,例如,CEI-25/28G、CEI-11G、PCI Express® (PCIe®) Gen 3.0、10GBASE-KR、万兆以太网、XAUI、CEI-6G、Serial RapidIO®、HD-SDI,等。
    使用内置高速背板连接器评估定制背板性能以及链路BER
    开发套件组成
    Stratix V GT版收发器SI开发套件包括:
    Stratix V GT开发板
    安装的器件
    5SGTMC7K3F40C2NES
    配置状态和设置单元
    JTAG
    板上USB-BlasterTM
    通过MAX® II器件和闪存进行快速被动并行(FPP)配置
    两个配置文件存储
    温度测量电路(管芯和环境温度)
    时钟
    50MHz、125MHz可编程振荡器(预设值:624 MHz、644.5 MHz、706.25MHz、875 MHz)
    SMA连接器,为收发器参考时钟提供外部差分时钟。
    SMA连接器,为FPGA架构提供外部差分时钟。
    SMA连接器,用于从FPGA的锁相环(PLL)输出引脚输出差分时钟。
    通用用户输入/输出
    10-/100-/1000-Mbps以太网PHY (RGMII),提供RJ-45 (铜)连接器。
    16x2字符LCD
    一个8位DIP开关
    8个用户LED
    4个用户按键
    存储器件
    128-megabyte (MB)同步闪存(主要用于存储FPGA配置)
    高速串行接口
    4个与MMPX连接器连接的全双工GTB (25.8 Gbps)收发器通道
    7个与SMA连接器连接的全双工GTB (12.5 Gbps)收发器通道
    连接微带线的短走线
    6个带状线通道,通道间所有走线长度均匹配。
    21个与背板连接器连接的全双工GXB收发器通道
    与Molex® Impact®连接器连接的7个通道
    与Amphenol® XCede®连接的7个通道
    与Tyco Strada® Whisper®(没有安装连接器)引脚连接的7个通道
    电源
    笔记本计算机直流输入
    电压余量
    Stratix V GT收发器SI开发套件软件组成
    Altera完整的设计套装(从Altera下载中心下载)
    Quartus II软件为Stratix V FPGA提供支持
    含一年许可
    Nios® II嵌入式设计套装
    MegaCore®知识产权(IP)库包括PCIe、三速以太网、串行数字接口(SDI),以及DDR3 SDRAM高性能控制器MegaCore IP。
    通过OpenCore Plus进行IP评估
    电路板更新入口
    提供Nios II网络服务器,支持系统远程更新。
    基于GUI的电路板测试系统
    通过JTAG与PC连接
    用户控制的PMA设置(预加重和均衡,等)
    状态指示(误码,BER,等)
    完整的文档
    用户指南
    参考手册
    电路板原理图和布板设计文件


    上一篇:【DK-100G-5SGXEA7N】Stratix V GX版100G开发套件

    下一篇:【DK-AS-5SGXEA7N】Stratix V高级系统开发电路板


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